Design and Implementation of a Prototype OpticalDe ection

We describe the design and implementation of a packet-switched ber optic interconnect prototype with a ShuueNet topology, intended for use in shared-memory multiprocessors. Coupled with existing latency-hiding mechanisms, it can reduce latency to remote memory locations. Nodes use deeection routing to resolve contention. Each node contains a processor, memory, pho-tonic switch, and packet routing processor. Payload remains in optical form from source to nal destination. Each host processor is a commercial workstation with FIFO interfaces between its bus and the pho-tonic switch. A global clock is distributed optically to each node to minimize skew. Component costs and network performance gures are presented for various node conngurations including bit-per-wavelength and ber-parallel packet formats. Our eeorts to implement and test a practical interconnect including real host computers distinguishes our work from previous theoretical and experimental work. We summarize obstacles we encountered and discuss future work.